FPGA Engineer - High Frequency Trading
Job Description
Job Description:
We are seeking a skilled FPGA Engineer to join our high-performance team in Chicago. In this role, you will design, implement, and optimize FPGA-based systems to support our ultra-low-latency trading strategies. You'll collaborate with traders and software engineers to develop cutting-edge solutions that provide a competitive edge in the market.
Responsibilities:
- Design and develop high-performance FPGA solutions for trading systems.
- Optimize hardware for ultra-low-latency data processing and communication.
- Collaborate with software engineers and traders to integrate FPGA solutions with trading platforms.
- Debug, test, and maintain FPGA designs to ensure reliability and performance.
- Stay updated on the latest FPGA technologies and apply them to improve system performance.
Job Requirements
Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience with FPGA design using Verilog, VHDL, or SystemVerilog.
- Proficiency in hardware design tools like Vivado, Quartus, or similar.
- Strong understanding of low-latency systems and high-frequency trading (HFT) concepts.
- Experience with network protocols (e.g., TCP/IP, UDP).
- Excellent problem-solving skills and attention to detail.
Preferred Skills:
- Familiarity with high-speed trading environments.
- Experience with C/C++ and Python for system integration.
- Knowledge of scripting for automation.
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Additional Information
Why Join Us?
- Work on cutting-edge technology in a dynamic trading environment.
- Competitive compensation and benefits package.
- Collaborative and innovative culture that values your expertise.
Target base salary of $150-$225K depending on a number of factors and will be able to receive an annual discretionary cash bonus which can be a significant portion of your total compensation.
Will also receive other benefits including:
- Health
- Dental
- Vision insurance
- 401(k) contributions
- Generous PTO, etc.